In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
Typically, the packages on which the integrated semiconductor chips are mounted include a substrate or other chip-mounting device. Substrates are parts that provide a package with mechanical base support and a form of electrical interface that would allow the external world to access the devices housed within the package.
When multiple chips are mounted within the same semiconductor package, routing problems may arise due to the different routing design of each individual chip. To solve this problem, an interposer is often used. An interposer is an electrical interface routing between one socket or connection to another. It is an intermediate layer often used for interconnection routing or as a ground/power plane. Sometimes the terms “substrate” and “interposer” are used to refer to the same thing.
A 3-dimentional (3D) integrated circuit package is a single integrated circuit package built by stacking silicon wafers and/or dies and interconnecting them so that they behave as a single device. A 3D package contains two or more chips stacked together so that the 3D package occupies less space. Each chip in a 3D package could be a conventional chip, a flip chip, or other chip so that the 3D package could have versatile functionalities.
A Package-on-Package (PoP) package is a 3D package in which fully tested packages, typically referred to as Known Good Packages (KGPs), are stacked on top of one another during the board mounting process. A conventional PoP package usually consists of a bottom package and a top package and has a two-tiered configuration. The bottom package is typically an ASIC or baseband chip and the top package may be other functional chip such as memory. Typically both the bottom package and the top package have a laminated substrate or interposer.
The modern trend of semiconductor manufacturing and packaging technology requires multiple chips with different functionalities such as radio-frequency (RF), logic, analog, base-band, and memory be packaged into a single integrated circuit system. Conventional PoP package is facing increasing challenge to accommodate more and more functional chips in a single package with tight space constraint. The conventional two-tiered configuration can no longer fulfill this purpose effectively.
Certain three-tiered Fan-in PoP package is experimented to address this problem. But it suffers from high substrate cost and high manufacturing complexity. Furthermore, some of the conventional PoP packaging techniques require forming via holes through the entire package to connect the top package to the bottom package, resulting in increased manufacturing complexity and cost.
Thus, a need still remains for accommodating the modern trend of semiconductor manufacturing and packaging, reducing the package footprint, increasing functionality integration, and increasing the packaging density. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.